Problem of the day
Tip 1 : MOST IMPORTANT- HAVE YOUR BASICS CLEAR! No amount of cross questioning should confuse you.
Tip 2 : Practise previous year GATE questions
Tip 3 : Have atleast a basic knowledge of any one of the hardware description languages- VERILOG or VHDL
Tip 1 : Be honest. Don't include an achievement/project that is not yours.
Tip 2 : Highlight your projects and do include an ongoing project if you have any.
The timing was from 4:30 pm to 6 pm, so it was quite convenient. The platform was good, the only problem I had was while attempting diagram based questions, as the interface was difficult to understand. The test had three types of questions- MCQ, subjective and diagram based. The major topics from which the question were asked were- sequential circuits(sequence detector), static timing analysis, digital design and computer architecture.
The timing for my interview was 9:30 pm and it went on for an hour. They asked me thorough questions from majorly two topics- CMOS and Digital System Design. Even if I was not able to answer certain questions,, they were happy to drop hints and then observed how I went further with the solution.
Design a JK flip flop using Nand gates. Assuming delays for the gates, find out the setup and hold times for the system
It was conducted around 11 am. HR round is not a thing to worry about if you are sitting for core companies, but don't miss the pre-placement talk of the company, they do ask about it. Other than that,I was just asked questions about my family and my prefered location.